VLSI數(shù)字信號處理系統(tǒng)設計與實現(xiàn)（英文版）

定　價：￥79.00

作　者：	（美）帕赫著
出版社：	機械工業(yè)出版社
叢編項：	經(jīng)典原版書庫
標　簽：	通信技術理論與基礎

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ISBN：	9787111123484	出版時間：	2003-10-01	包裝：	膠版紙
開本：	16	頁數(shù)：	784	字數(shù)：

內(nèi)容簡介

　　視頻壓縮，無線通信，全球定位、雷達影像……在DSP的廣泛應用領域內(nèi)，怎樣設計出高速、精巧的VLSI系統(tǒng)？并行處理、流水線。ASIC、可編程數(shù)字信號處理器，為實現(xiàn)DSP算法，技術與工具怎樣結(jié)合才能更加完美？本書將為您提供答案。它既是折疊、異步流水線等技術的資源寶庫，同時也是方向標，通過大量的實踐經(jīng)驗指明了進入VLSI王國的捷徑。本書特點：通過上百張圖片對不同的DSP算法進行解釋每章后的習題將技術與現(xiàn)實緊密結(jié)合起來適用面廣，可作為《VlSI數(shù)字信號處理體系結(jié)構(gòu)》或《高性能VLSI系統(tǒng)設計》等課程的教材提供有無線。有線。多媒體通信多個領域內(nèi)的技術與經(jīng)驗作者簡介：KeshabK．Parhi于印度理工學院獲得工學學士學位；1984年于賓夕法尼亞大學獲得電子與電氣工程碩士學位：1988年在加利福尼亞大學伯克利分校獲得博士學位。自1988年以來，一直執(zhí)教于明尼蘇達大學電子和計算機工程系，最近剛剛獲得McKnight大學杰出教授榮譽稱號。他的研究方向包括：并發(fā)算法，通信架構(gòu)設計、信號和圖像處理系統(tǒng)。數(shù)字集成電路、VLSI數(shù)字濾波器等。他是IEEE成員。作為主席，他主持了IEEE1995VLSI數(shù)字處理研討會。IEEE1996特殊應用系統(tǒng)、體系結(jié)構(gòu)和處理器研討會以及IEEE2002數(shù)字處理的設計與實現(xiàn)研討會。

作者簡介

　　KeshabK.Parhi于印度理工學院獲得工學學士學位：1984年于賓夕法尼亞大學獲得電子工程碩士學位：1988年在加利福尼亞大學伯克利分校獲得博士學位。自1988年以來，一直執(zhí)教于昆尼蘇達大學電子和計算機工程系，最近剛剛獲得McKnight大學杰出教授榮譽稱號。他的研究方向包括：并發(fā)算法、通信架構(gòu)設計、信號和圖像處理系統(tǒng)、數(shù)字集成電路、VLSI數(shù)字濾波器等。他是IEEE成員。作為主席，他主持了IEEE1995VLSI數(shù)字處理研討會、IEEE1996特殊應用系統(tǒng)、體系結(jié)構(gòu)和處理器研討會以及IEEE2002數(shù)字處理的設計與實現(xiàn)研討會。

圖書目錄

Preface
Introduction to Digital Signal Processing Systems
1.1  Introduction
1.2  Typical DSP Algorithms
1.3  DSP Application Demands and Scaled CMOS Technologies
1.4  Representations of DSP Algorithms
1.5  Book Outline
References
2  Iteration Bound
2.1  Introduction
2.2  Data-Flow Graph Representations
2.3  Loop Bound and Iteration Bound
2.4  Algorithms for Computing Iteration Bound
2.5  Iteration Bound of Multirate Data-Flow Graphs
2.6  Conclusions
2.7  Problems
References
3  Pipelining and Parallel Processing
3.1  Introduction
3.2  Pipelining of FIR Digital Filters
3.3  Parallel Processing
3.4  Pipelining and Parallel Processing for Low Power
3.5  Conclusions
3.6  Problems
References
4  Retiming
4.1 Introduction
4.2  Definitions and Properties
4.3  Solving Systems of Inequalities
4.4  Retiming Techniques
4.5  Conclusions
4.6  Problems
References
5  Unfolding
5.1  Introduction
5.2  An Algorithm for Unfolding
5.3  Properties of Unfolding
5.4  Critical Path, Unfolding, and Retiming
5.5  Applications of Unfolding
5.6  Conclusions
5.7  Problems
References
6  Folding
6.1  Introduction
6.2  Folding Transformation
6.3  Register Minimization Techniques
6.4  Register Minimization in Folded Architectures
6.5  Folding of Multirate Systems
6.6  Conclusions
6.7  Problems
References
7 .Systolic Architecture Design
7.1  Introduction
7.2  Systolic Array Design Methodology
7.3  FIR Systolic Arrays
7.4  Selection of Scheduling Vector
7.5  Matrix-Matrix Multiplication and 2D Systolic Array Design
7.6  Systolic Design for Space Representations Containing Delays
7.7  Conclusions
7.8  Problems
References
8  Fast Convolution
8.1  Introduction
8.2  Cook-Toom Algorithm
8.3  Winograd Algorithm
8.4  Iterated Convolution
8.5  Cyclic Convolution
8.6  Design of Fast Convolution Algorithm by Inspection
8.7  Conclusions
8.8  Problems
References
9  Algorithmic Strength Reduction in Filters and Transforms
9.1  Introduction
9.2  Parallel FIR Filters
9.3  Discrete Cosine Transform and Inverse DCT
9.4  Parallel Architectures for Rank-Order Filters
9.5  Conclusions
9.6  Problems
References
10 Pipelined and Parallel Recursive and Adaptive Filters
10.1 Introduction
10.2 Pipeline Interleaving in Digital Filters
10.3 Pipelining in 1st-Order IIR Digital Filters
10.4 Pipelining in Higher-Order IIR Digital Filters
10.5 Parallel Processing for IIR filters
10.6 Combined Pipelining and Parallel Processing for IIR Filters
10.7 Low-Power IIR Filter Design Using Pipelining and Parallel Processing
10.8 Pipelined Adaptive Digital Filters
10.9 Conclusions
10.10 Problems
References
11 Scaling and Roundoff Noise
11.1 Introduction
11.2 Scaling and Roundoff Noise
11.3 State Variable Description of Digital Filters
11.4 Scaling and Roundoff Noise Computation
11.5 Roundoff Noise in Pipelined IIR Filters
11.6 Roundoff Noise Computation Using State Variable Description
11.7 Slow-Down, Retiming, and Pipelining
11.8 Conclusions
11.9 Problems
References
12 Digital Lattice Filter Structures
12.1 Introduction
12.2 Schur Algorithm
12.3 Digital Basic Lattice Filters
12.4 Derivation of One-Multiplier Lattice Filter
12.5 Derivation of Normalized Lattice Filter
12.6 Derivation of Scaled-Normalized Lattice Filter
12.7 Roundoff Noise Calculation in Lattice Filters
12.8 Pipelining of Lattice IIR Digital Filters
12.9 Design Examples of Pipelined Lattice Filters
12.10 Low-Power CMOS Lattice IIR Filters
12.11 Conclusions
12.12 Problems
References
13 Bit-Level Arithmetic Architectures
13.1 Introduction
13.2 Parallel Multipliers
13.3 Interleaved Floor-plan and Bit-Plane-Based Digital Filters
13.4 Bit-Serial Multipliers
13.5 Bit-Serial Filter Design and Implementation
13.6 Canonic Signed Digit Arithmetic
13.7 Distributed Arithmetic
13.8 Conclusions
13.9 Problems
References
14 Redundant Arithmetic
14.1 Introduction
14.2 Redundant Number Representations
14.3 Carry-Free Radix-2 Addition and Subtraction
14.4 Hybrid Radix-4 Addition
14.5 Radix-2 Hybrid Redundant Multiplication Architectures
14.6 Data Format Conversion
14.7 Redundant to Nonredundant Converter
14.8 Conclusions
14.9 Problems
References
15 Numerical Strength Reduction
15.1 Introduction
15.2 Subexpression Elimination
15.3 Multiple Constant Multiplication
15.4 Subexpression Sharing in Digital Filters
15.5 Additive and Multiplicative Number Splitting
15.6 Conclusions
15.7 Problems
References
16 Synchronous, Wave, and Asynchronous Pipelines
16.1 Introduction
16.2 Synchronous Pipelining and Clocking Styles
16.3 Clock Skew and Clock Distribution in Bit-Level Pipelined VLSI Designs
16.4 Wave Pipelining
16.5 Constraint Space Diagram and Degree of Wave Pipelining
16.6 Implementation of Wave-Pipelined Systems
16.7 Asynchronous Pipelining
16.8 Signal Transition Graphs
16.9 Use of STG to Design Interconnection Circuits
16.10 Implementation of Computational Units
16.11 Conclusions
16.12 Problems
References
17 Low-Power Design
17.1 Introduction
17.2 Theoretical Background
17.3 Scaling Versus Power Consumption
17.4 Power Analysis
17.5 Power Reduction Techniques
17.6 Power Estimation Approaches
17.7 Conclusions
17.8 Problems
References
18 Programmable Digital Signal Processors
18.1 Introduction
18.2 Evolution of Programmable Digital Signal Processors
18.3 Important Features of DSP Processors
18.4 DSP Processors for Mobile and Wireless Communications
18.5 Processors for Multimedia Signal Processing
18.6 Conclusions
References
Appendix A: Shortest Path Algorithms
A.1  Introduction
A.2  The Bellman-Ford Algorithm
A.3  The Floyd-Warshall Algorithm
A.4  Computational Complexities
References
Appendix B: Scheduling and Allocation Techniques
B.1  Introduction
B.2  Iterative/Constructive Scheduling Algorithms
B.3  Transformational Scheduling Algorithms
B.4  Integer Linear Programming Models
Appendix C: Euclidean GCD Algorithm
C.1  Introduction
C.2  Euclidean GCD Algorithm for Integers
C.3  Euclidean GCD Algorithm for Polynomials
Appendix D: Orthonormality of Schur Polynomials
D.1  Orthogonality of Schur Polynomials
D.2  Orthonormality of Schur Polynomials
Appendix E: Fast Binary Adders and Multipliers
E.1  Introduction
E.2  Multiplexer-Based Fast Binary Adders
E.3  Wallace Tree and Dadda Multiplier
References
Appendix F: Scheduling in Bit-Serial Systems
F.1  Introduction
F.2  Outline of the Scheduling Algorithm
F.3  Minimum Cost Solution
F.4  Scheduling of Edges with Delays
References
Appendix G: Coefficient Quantization in FIR Filters
G.1  Introduction
G.2  NUS Quantization Algorithm
References
Index